发明名称 CLOCK DIVIDER
摘要 <p>Provided according to the present invention is a circuit including a logical circuit. The logical circuit is formed to be operated without inputs from a first clock signal. Also, the logical circuit is formed to generate a second clock signal by dividing frequency of the first clock signal based on a logical combination of a first pattern provided by the first circuit operated by the first clock signal a second pattern provided by a second circuit operated by the first clock signal.</p>
申请公布号 KR20150090861(A) 申请公布日期 2015.08.06
申请号 KR20150014369 申请日期 2015.01.29
申请人 MARVELL WORLD TRADE LTD. 发明人 LIFSHITZ ELAD
分类号 H03K23/40;H03K23/54 主分类号 H03K23/40
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