| 摘要 |
The invention proposes a scan sequential element device (scan flip-flop or scan latch) for integrated circuit the device (30) receiving as input three respective input signals D, S1I, SE and at least one clock signal CLK, and comprising an output Q. The device comprises: - a system sequential element (300) comprising an input driven by a first input signal (D) of the device, an input driven by a second input signal (SE) of the device, and an input driven by one of the clock signals (CLK) received as input by the device, and - a phantom sequential element (310) comprising an input driven by the third input signal (S1I) of the device, an input driven by the second input signal (SE) of the device and an input driven by one of the clock signals (CLK) received as input by the device, the device being configured so that the first input signal D is propagated to the output Q of the device through the system sequential element (300) when the second input signal SE is inactivated, and the third input signal (SI) is propagated to the output Q of the device (30) through the phantom sequential element (310) and the system sequential element (300), when the second input signal (SE) is activated, the propagation of the third input signal (SI) from the phantom sequential element (310) to the system sequential element (300) being carried out in an asynchronous manner, that is to say decorrelated from the clock signals (CLK). |
