| 摘要 |
<p>The invention relates to a logic gate (30) for the symmetrization of at least two input signals, which comprises a non-inverting input (11), an inverting input (12) and an output (19). The value present on the output (19) corresponds to the inverse of the value present on the inverting input (12). According to the invention, the output (19) is activated only when the value present on the non-inverting input (11) likewise corresponds to the inverse of the value present on the inverting input (12). The invention further relates to a logic gate system which comprises at least two logic gates (30).</p> |
