| 摘要 |
There is provided with an information processing apparatus comprising a DRAM, a memory controller configured to access the DRAM, and a bus master configured to send, to the memory controller, an access request to the DRAM, the bus master comprises a transmission unit configured to transmit, to the memory controller, using a signal indicating a type of burst access which is requested of the memory controller by the bus master, an instruction to designate that an auto-precharge operation is not to be performed after accessing the first address, and an instruction to designate that an auto-precharge operation is to be performed after accessing the first address. |
