| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide a technology capable of improving connection reliability between bump electrodes of a semiconductor chip and wirings of a mounting substrate; specifically, technology capable of improving connection reliability between the bump electrodes and the wirings formed on a glass substrate by ensuring flatness of the bump electrodes even when the wirings are arranged in an uppermost wiring layer below the bump electrodes.SOLUTION: A semiconductor device comprises wirings L1 including a power supply wiring and a signal wiring and dummy patterns DP which are formed in an uppermost wiring layer immediately below a non-overlap region Y of a bump electrode BP1. The dummy patterns DP are arranged so as to fill spaces between the wirings L1 to reduce irregularity caused by the wirings L1 and the spaces in the uppermost wiring layer. Further, planarization by a CMP method is performed on a surface protection film formed so as to cover the uppermost wiring layer.</p> |
