| 摘要 |
The present invention relates to bit interleaving and de-interleaving of quasi-cyclic low-density parity-check (QC-LDPC) codes and discloses a bit interleaver that allows for a particularly efficient hardware implementation due to its high degree of parallelism. This is achieved by selecting a subset of the cyclic blocks of the QC-LDPC codeword such that the number of selected cyclic blocks times an integer F divided by the number of bits per constellation word M yields an integer value, wherein F is a divisor of M. Then, a permutation for mapping the bits of the selected cyclic blocks to a sequence of constellation words is constructed that can be performed independently for each of floor(F·N/M) sections of the codeword, wherein N is the number of cyclic blocks within the codeword and M the number of bits per constellation word. According to a further aspect of the present invention, the selection of the cyclic blocks is performed on the basis of an importance level of the bits contained therein. |
