Semiconductor memory device

摘要

According to one embodiment, a semiconductor memory device includes a plurality of cell array blocks and a control circuit. The control circuit sets a selected bit line to have 0 volt, applies a first electric potential which is higher than 0 volt to a selected word line, applies a second electric potential which is higher than 0 volt and lower than the first electric potential to non-selected word lines other than the selected word line, applies a third electric potential which is 0 volt or more and lower than the second electric potential to a non-selected bit line adjacent to the selected bit line in an adjacent cell array block, applies the second electric potential to non-selected bit lines other than the non-selected bit line to which the third electric potential is applied, and changes a resistance status of the resistance variable film of the selected memory cell.

主权项

1. A semiconductor memory device, comprising:
a plurality of cell array blocks including a plurality of bit lines extending in a first direction, a plurality of word lines extending in a second direction intersecting with the first direction, and a plurality of memory cells provided between the bit lines and the word lines at cross-points of the bit lines and the word lines and including a resistance variable film, the cell array blocks including a first cell array block, a second cell array block adjacent to the first cell array block in the first direction, a third cell array block adjacent to the first cell array block on an opposite side to the second cell array block, the bit lines including a plurality of first bit lines and a plurality of second bit lines, the first bit lines shared between the first cell array block and the second cell array block, and not shared between the first cell array block and the third cell array block, the second bit lines shared between the first cell array block and the third cell array block, and not shared between the first cell array block and the second cell array block; and a control circuit that sets a selected bit line connected to a selected memory cell selected from the plurality of memory cells to have 0 volt, applies a first electric potential which is higher than 0 volt to a selected word line connected to the selected memory cell, applies a second electric potential which is higher than 0 volt and lower than the first electric potential to non-selected word lines other than the selected word line, applies a third electric potential which is 0 volt or more and lower than the second electric potential to a non-selected bit line adjacent to the selected bit line in an adjacent cell array block that is adjacent to the selected cell array block including the selected memory cell in the first direction and shares the selected bit line with the selected cell array block, applies the second electric potential to non-selected bit lines other than the non-selected bit line to which the third electric potential is applied, and changes a resistance status of the resistance variable film of the selected memory cell.