发明名称 |
Two-stage power delivery architecture |
摘要 |
A two-stage power delivery network includes a voltage regulator and an interposer. The interposer includes a packaging substrate having an embedded inductor. The embedded inductor includes a set of traces and a set of through substrate vias at opposing ends of the traces. The interposer is coupled to the voltage regulator. The two-stage power delivery network also includes a semiconductor die supported by the packaging substrate. The two-stage power delivery network also includes a capacitor that is supported by the packaging substrate. The capacitor is operable to provide a decoupling capacitance associated with the semiconductor die and a capacitance to reduce a switching noise of the voltage regulator. |
申请公布号 |
US9101068(B2) |
申请公布日期 |
2015.08.04 |
申请号 |
US201313830033 |
申请日期 |
2013.03.14 |
申请人 |
QUALCOMM INCORPORATED |
发明人 |
Yun Changhan;Carobolante Francesco;Zuo Chengjie;Kim Jonghae;Velez Mario Francisco;Smith Lawrence D.;Nowak Matthew M. |
分类号 |
H05K7/00;H05K7/10;H05K1/02;H05K1/16;H01L23/498 |
主分类号 |
H05K7/00 |
代理机构 |
Seyfarth Shaw LLP |
代理人 |
Seyfarth Shaw LLP |
主权项 |
1. A two-stage power delivery network, comprising:
a voltage regulator; an interposer comprising a packaging substrate having an embedded inductor including a plurality of traces and a plurality of through substrate vias at opposing ends of the plurality of traces, the interposer coupled to the voltage regulator; a semiconductor die supported by the packaging substrate; and a metal-insulator-metal capacitor directly on the packaging substrate and embedded within a protective layer of the interposer, the metal-insulator-metal capacitor operable to provide a decoupling capacitance associated with the semiconductor die and a capacitance to reduce a switching noise of the voltage regulator. |
地址 |
San Diego CA US |