Controlling an order for processing data elements during vector processing

摘要

A data processing apparatus includes a register bank having a plurality of registers for storing vectors being processed; a pipelined processor for processing the stream of vector instructions; the pipelined processor comprising circuitry configured to detect data dependencies for the vectors processed by the stream of vector instructions and stored in the plurality of registers and to determine constraints on timing of execution for the vector instructions such that no register data hazards arise. Register data hazards arise where two accesses to a same register, at least one of said accesses being a write, occur in an order different to an order of said instruction stream such that an access occurring later in said instruction stream starts before an access occurring earlier in said instruction stream has completed. The pipelined processor includes data element hazard determination circuitry.

主权项

1. A data processing apparatus for processing a stream of vector instructions for performing operations on vectors, said vectors each comprising a plurality of data elements, said data processing apparatus comprising:
a register bank comprising a plurality of registers for storing said vectors being processed; a pipelined processor for processing said stream of vector instructions; said pipelined processor comprising circuitry configured to detect data dependencies for said vectors processed by said stream of vector instructions and stored in said plurality of registers and to determine constraints on timing of execution for said vector instructions such that no register data hazards arise, said register data hazards arising where two accesses to a same register, at least one of said accesses being a write, occur in an order different to an order of said instruction stream such that an access occurring later in said instruction stream starts before an access occurring earlier in said instruction stream has completed; said pipelined processor comprising data element hazard determination circuitry configured to determine for at least some of said data elements within vectors where data dependencies have been identified, whether said data dependencies identified for said vectors exist for each of said at least some of said data elements, and if not to relax said determined constraints on timing of execution for an instruction processing said data element.