Data receiver, clock generation device, and method for controlling data receiver

摘要

A data receiver includes a writing unit that receives transmission data including live data and excessive data for adjusting a signal length to store the live data in a storage unit, an AND circuit that generates a first signal indicating the positions of the live data and the excessive data in the signal length of the transmission data, a signal converting unit that generates a second signal indicating positions at which positions of the excessive data in the first signal are rearranged at certain intervals in the signal length, a digital phase locked loop (DPLL) unit that smoothes the positions of the live data in the second signal to generate a third signal indicating the timing to read the live data in the signal length, and a reading unit that reads the live data stored in the storage unit by using the third signal.

主权项

1. A data receiver comprising:
a data receiving unit that receives transmission data including live data that is actual data to be transmitted or received and excessive data for adjusting a signal length, and stores the live data in a storage unit; a first signal generating unit that generates a first signal indicating positions of the live data and the excessive data in the signal length of the transmission data; a signal converting unit that generates a second signal indicating positions at which positions of the excessive data in the first signal are rearranged at certain intervals in the signal length; a digital phase locked loop (DPLL) unit that smoothes the positions of the live data in the second signal to generate a third signal indicating a timing to read the live data in the signal length; and a reading unit that reads the live data stored in the storage unit by using the third signal.