Programmable array of silicon nanowire field effect transistor and method for fabricating the same

摘要

The present invention discloses a hexagonal programmable array based on a silicon nanowire field effect transistor and a method for fabricating the same. The array includes a nanowire device, a nanowire device connection region and a gate connection region, wherein, the nanowire device has a cylinder shape, and includes a silicon nanowire channel, a gate dielectric layer, and a gate region, the nanowire channel being surrounded by the gate dielectric layer, and the gate dielectric layer being surrounded by the gate region; the nanowire devices are arranged in a hexagon shape to form programming unit, the nanowire device connection region is a connection node of three nanowire devices and secured to a silicon supporter. The present invention can achieve a complex control logic of interconnections and is suitable for a digital/analog and a mixed-signal circuit having a high integration degree and a high speed.

主权项

1. A hexagonal programmable array based on a silicon nanowire field effect transistor, the hexagonal programmable array comprising:
a nanowire device having a nanowire device connection region and a gate connection region, the nanowire device connection region being defined where three nanowire devices are connected; wherein the nanowire device has a floated cylinder shape and includes a silicon nanowire channel, a gate dielectric layer and a gate layer, the entire silicon nanowire channel being surrounded by the gate dielectric layer, and the gate dielectric layer being surrounded by the gate layer, wherein the silicon nanowire channel, the gate dielectric layer and the gate layer have an identical length, which is in a range of 5 nm-1 μm; wherein the nanowire devices are arranged in hexagon structures to form programming units each corresponding to one hexagon structure, a common nanowire device is shared by adjacent programming units, and a central portion of each of the programming units is a hollow region; wherein the nanowire device connection region is connected to the silicon nanowire channel while being used as a source or a drain of the nanowire device; wherein the nanowire device connection region is secured to a silicon supporter underneath the nanowire device connection region; and wherein a connection for the gate layers of the plurality of nanowire devices is provided by the gate connection region, so that the plurality of nanowire devices form a gate-sharing structure.