发明名称 Three-dimensional system-level packaging methods and structures
摘要 A 3D system-level packaging method includes providing a packaging substrate, forming a glue layer on the substrate, and attaching a first chip layer at an opposite side of a functional surface of the first chip layer on the packaging substrate through the glue layer. The method also includes forming a first sealant layer on the packaging substrate at a same side attached with the first chip layer and exposing bonding pads of the first chip layer. The method also includes forming first vias in the first sealant layer, forming first vertical metal wiring in the first vias, and forming a first horizontal wiring layer on the sealant layer interconnecting the first chip layer and the first vertical metal wiring. Further, the method includes forming a plurality of package layers on the first sealant layer, and each of the plurality of package layers includes a chip layer, a sealant layer covering the chip layer, and vertical metal wiring and a horizontal wiring layer interconnecting adjacent package layers.
申请公布号 US9099448(B2) 申请公布日期 2015.08.04
申请号 US201213984967 申请日期 2012.03.22
申请人 NANTONG FUJITSU MICROELECTRONICS CO., LTD. 发明人 Tao Yujuan;Shi Lei;Wang Honghui
分类号 H01L23/48;H01L23/52;H01L23/02;H01L23/485;H01L25/00;H01L21/58;H01L23/538;H05K1/18 主分类号 H01L23/48
代理机构 Anova Law Group, PLLC 代理人 Anova Law Group, PLLC
主权项 1. A method for 3D system-level packaging, comprising: providing a packaging substrate; forming a glue layer on the substrate; attaching a first chip layer at an opposite side of a functional surface of the first chip layer on the packaging substrate through the glue layer; forming a first sealant layer on the packaging substrate at a same side attached with the first chip layer and exposing bonding pads of the first chip layer; forming first vias in the first sealant layer; forming first vertical metal wiring in the first vias; forming a first horizontal wiring layer on the sealant layer interconnecting the first chip layer and the first vertical metal wiring; and forming a plurality of package layers on the first sealant layer, wherein: each of the plurality of package layers includes a chip layer, a sealant layer covering the chip layer, and vertical metal wiring and a horizontal wiring layer interconnecting adjacent package layers,each sealant layer of the plurality of package layers is formed on a top of a sealant layer of a preceding package layer, andeach sealant layer of the plurality of package layers and the sealant layer of the preceding package layer are in contact with each other.
地址 Nantong CN