发明名称 |
QC-LDPC convolutional codes enabling low power trellis-based decoders |
摘要 |
A low-density parity check (LDPC) encoding method for increasing constraint length includes determining a LDPC code block H-matrix including a systematic submatrix (Hsys) of input systematic data and a parity check submatrix (Hpar) of parity check bits. The method includes diagonalizing the parity check submatrix (Hpar). The method includes identifying a set of rows of the H-matrix that form a complete set of the input systematic data. The method includes selecting an input bit granularity (γ) and encoding latency. The method further includes obtaining a quasi-cyclic LDPC (QC-LDPC) convolutional code H-Matrix. Further, the method includes combining the set of rows into a single row. |
申请公布号 |
US9100052(B2) |
申请公布日期 |
2015.08.04 |
申请号 |
US201314033229 |
申请日期 |
2013.09.20 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
Pisek Eran |
分类号 |
H03M13/00;H03M13/25;H03M13/03;H03M13/11;H03M13/41 |
主分类号 |
H03M13/00 |
代理机构 |
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代理人 |
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主权项 |
1. A low-density parity check (LDPC) encoding method for increasing constraint length, the method comprising:
determining an LDPC code block H-matrix including a systematic submatrix (Hsys) of input systematic data and a parity check submatrix (Hpar) of parity check bits; diagonalizing the parity check submatrix (Hpar); identifying a set of rows of the LDPC code block H-matrix that form a complete set of the input systematic data; selecting an input bit granularity (γ) and encoding latency; obtaining a quasi-cyclic LDPC (QC-LDPC) convolutional code H-Matrix; and combining the set of rows into a single row. |
地址 |
Suwon-Si KR |