Clock generation circuit and semiconductor device provided therewith

摘要

It is an object of the present invention to solve a problem that malfunction of communication is generated by varying a frequency of a clock due to noise from outside in a case where there is no supplied signal in a circuit which performs negative feedback control so that the supplied signal and the feedback signal can maintain a fixed phase relationship between the signals. The present invention provides a configuration including a PLL circuit and an oscillator circuit, where a switch for switching an output between a signal from the PLL circuit and a signal from the oscillator circuit to the signal output portion is provided to switch from a connection to the PLL circuit to a connection to the oscillator circuit in a case where there is no received signal.

主权项

1. A clock generation circuit comprising:
a PLL circuit; an oscillator circuit; and a determination circuit, wherein, in a signal input portion, the determination circuit is a circuit which determines a first period from receiving a reception start signal to receiving a reception end signal and a second period except for a period from receiving a reception start signal to receiving a reception end signal by the clock generation circuit, and wherein a switch for selecting an input signal in the first period to be inputted to a signal input portion of the PLL circuit and selecting a signal of the oscillator circuit in the second period to be inputted to the signal input portion of the PLL circuit is provided.