Multiple bitcells tracking scheme semiconductor memory array

摘要

A memory array includes a memory segment having at least one memory bank. The at least one memory bank includes an array of memory cells, and wherein at least two first read tracking cells are disposed in a read tracking column of the at least one memory bank. The memory array further includes a read tracking circuit coupled to the at least two first read tracking cells. Outputs of the at least two first read tracking cells are connected to a tracking bit connection line (TBCL). A tracking circuit connected to the TBCL is configured to output a tracking-cells output signal to generate a global tracking result signal to a memory control circuitry. The memory control circuitry is configured to reset a memory clock based on the global tracking result signal.

主权项

1. A memory array, comprising:
a memory segment having at least one memory bank, wherein the at least one memory bank includes an array of memory cells, and wherein at least two first read tracking cells are disposed in a read tracking column of the at least one memory bank; and a read tracking circuit coupled to the at least two first read tracking cells, wherein outputs of the at least two first read tracking cells are connected to a tracking bit connection line (TBCL), wherein a tracking circuit connected to the TBCL is configured to output a tracking-cells output signal to generate a global tracking result signal to a memory control circuitry, wherein the memory control circuitry is configured to reset a memory clock based on the global tracking result signal.