Digital serial multiplier

摘要

A multiplier of a binary number A by a binary number B may be configured to add each term AiBj with a left shift by i+j bits, where Ai is the bit of weight i of number A, and Bj the bit of weight j of number B. The multiplier may include a first counter associated with the number A and may count modulo n and be paced by a clock. The multiplier may include a second counter associated with the number B and paced by the clock. Switching circuitry may produce the terms AiBj by taking the content of the first and second counters respectively as weights i and j. Shifting circuitry is configured to shift the content of one of the first and second counters when the other counter has achieved a revolution.

主权项

1. A multiplier for multiplying a binary number A of n bits by a binary number B of p bits and configured to add each term AiBj with a left shift by i+j bits, where Ai is a bit of weight i of the binary number A, and Bj a bit of weight j of the binary number B, with i varying between 0 and n−1, and j varying between 0 and p−1, the multiplier comprising:
a first counter associated with the binary number A and configured to count modulo n and be clocked by a clock; a second counter associated with the binary number B and configured to be clocked by the clock; switching circuitry configured to sequentially produce terms AiBj by at least defining the weights i and j based upon contents of said first and second counters respectively; and shifting circuitry configured to shift the content of one of said first and second counters by an increment when the other of said first and second counters has executed a revolution.