Process for fabricating an enhancement mode heterojunction transistor

摘要

A method for fabricating a heterojunction field-effect transistor includes implanting p-type dopants form an implanted area in a first layer of III-V semiconductor alloy, removing an upper part of the first layer and of the implanted area by maintaining vapor phase epitaxy conditions, stopping the removal when the density of the dopant at the upper face of the implanted area is maximal, forming a second layer of III-V semiconductor alloy by vapor phase epitaxy on the implanted area and on the first layer, forming a third layer of III-V semiconductor alloy by vapor phase epitaxy in order to form an electron gas layer at the interface between the third layer and the second layer, and forming a control gate on the third layer plumb with the implanted area.

主权项

1. A method for fabricating a heterojunction field-effect transistor, said method comprising:
implanting p-type dopants in order to form an implanted area in a first layer of a III-V semiconductor alloy, removing an upper part of said first layer and of said implanted area by maintaining vapor phase epitaxy conditions, stopping said removing when a density of said p-type dopants at an uppermost face of said implanted area is maximal, forming a second layer of a III-V semiconductor alloy by vapor phase epitaxy on said implanted area and on said first layer, forming a third layer of a III-V semiconductor alloy by vapor phase epitaxy in order to form an electron gas layer at an interface between said third layer and said second layer, and forming a control gate on said third layer plumb with said implanted area.