Semiconductor device having vertical channels and method of manufacturing the same

摘要

A method of manufacturing a semiconductor device which can prevent leakage current caused by gate electrodes intersecting element isolation layers in a major axis of an active region, and which further has vertical channels to provide a sufficient overlap margin, and a semiconductor device manufactured using the above method. The device includes gate electrodes formed on element isolation layers that are disposed between active regions and have top surfaces that are higher than the top surfaces of the active regions. Since the gate electrodes are formed on the element isolation layers, leakage current in a semiconductor substrate is prevented. In addition, the gate electrodes are formed using a striped shape mask pattern, thereby obtaining a sufficient overlap margin compared to a contact shape or bar shape pattern.

主权项

1. A semiconductor device comprising:
a first active region protruding from a surface of a semiconductor substrate, wherein the first active region includes a first surface spaced apart from the surface of the semiconductor substrate; a second active region protruding from the surface of the semiconductor substrate, wherein the second active region includes a second surface spaced apart from the surface of the semiconductor substrate, and wherein the first and second active regions are aligned in a first direction; an isolation layer on the surface of the semiconductor substrate, wherein the isolation layer includes first and second portions that are recessed relative to the first surface of the first active region, wherein the first and second portions are on opposite sides of the first active region, wherein the isolation layer includes a third portion between the first and second active regions, and wherein the first and second portions of the isolation layer are recessed relative to the third portion of the isolation layer; an electrode on the first and second portions of the isolation layer and on the first active region, wherein the electrode extends in a second direction different than the first direction; a conductive pattern on the third portion of the isolation layer between the first and second active regions, wherein the conductive pattern extends in the second direction; and a gate insulation layer between the electrode and first active region.