Clock distribution network for 3D integrated circuit

摘要

Exemplary embodiments of the invention are directed to systems and method for designing a clock distribution network for an integrated circuit. The embodiments identify critical sources of clock skew, tightly control the timing of the clock and build that timing into the overall clock distribution network and integrated circuit design. The disclosed embodiments separate the clock distribution network (CDN), i.e., clock generation circuitry, wiring, buffering and registers, from the rest of the logic to improve the clock tree design and reduce the area footprint. In one embodiment, the CDN is separated to a separate tier of a 3D integrated circuit, and the CDN is connected to the logic tier(s) via high-density inter-tier vias. The embodiments are particularly advantageous for implementation with monolithic 3D integrated circuits.

主权项

1. A non-transitory computer readable medium having instructions stored thereon that when executed by a computer performs a method of developing a clock distribution network for an integrated circuit, the method comprising:
capturing sources of clock skew including timing mismatches between clock sinks; moving the clock sinks to a clock distribution network; synthesizing a behavioral description of the integrated circuit and said sources of clock skew to generate a 2D layout comprising the clock distribution network and combinational logic; separating said clock distribution network from said combinational logic and locating said clock distribution network to a first area of the integrated circuit; determining vias to provide via connections between the clock distribution network and the combinational logic, where the via connections are where the clock sinks were located before the step of moving the clock sinks; and floorplanning said combinational logic of said first area.