发明名称 Configurable bus
摘要 A configurable bus includes a plurality of bus segments. The configurable bus also includes two or more pluralities of input/output (I/O) ports. Each bus segment is coupled to at least one of the pluralities of I/O ports. Also coupled to the bus segments is a cross-couple unit that is configurable to selectively couple any of the bus segments together.
申请公布号 US9098641(B1) 申请公布日期 2015.08.04
申请号 US200711698660 申请日期 2007.01.25
申请人 Cypress Semiconductor Corporation 发明人 Kutz Harold;Snyder Warren S.;Williams Timothy J.;Thiagarajan Eashwar
分类号 G06F13/00;G06F13/40;G06F15/173 主分类号 G06F13/00
代理机构 代理人
主权项 1. A device comprising: an analog block array; a first analog bus segment coupled to the analog block array; a second analog bus segment coupled to the analog block array; a third analog bus segment coupled to the analog block array; a fourth analog bus segment, coupled to the analog block array; a first I/O pin selectively couplable to the first analog bus segment; a second I/O pin selectively couplable to the second analog bus segment; a third I/O pin selectively couplable to the third analog bus segment; a fourth I/O pin selectively couplable to the fourth analog bus segment; a first switch configured to selectively propogate a first analog signal on the first analog bus segment to the second analog bus segment; a second switch configured to selectively propogate a second analog signal on the first analog bus segment to the third analog bus segment; a third switch configured to selectively propogate a third analog signal on the second analog bus segment to the fourth analog bus segment; a fourth switch configured to selectively propogate a fourth analog signal on the third analog bus segment to the fourth analog bus segment; wherein, in a first mode of operation, the first, second, third, and fourth switches are open,in a second mode of operation, the first switch is closed, andin a third mode of operation, the second switch is closed.
地址 San Jose CA US
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