| 摘要 |
PROBLEM TO BE SOLVED: To provide a CV conversion circuit designed to reduce power consumption while maintaining a processing time for CV conversion and capable of reducing noise.SOLUTION: A second sample-and-hold circuit 14 samples-and-holds, in synchronism with two consecutive sampling periods of a first sample-and-hold circuit 12, a positive-phase output voltage VOp and an opposite-phase output voltage VOn of a differential amplifier 15 sampled-and-held by the first sample-and-hold circuit 12, simultaneously in a second capacitive element Cout3. Next, the second sample-and-hold circuit 14 connects, in another sampling period, a second capacitive element Cout3, in which electric charges were accumulated previously, to a positive-phase capacitive element Cout1 and an opposite-phase capacitive element Cout2 of the first sample-and-hold circuit 12 immediately before the positive-phase and opposite-phase capacitive elements Cout1, Cout2 are held at a desired level. At this time, the differential amplifier 15 has a load capacity connected to its output increased and its bandwidth narrowed. |
