| 摘要 |
PROBLEM TO BE SOLVED: To provide a programmable controller subject to little influence due to cache invalidation at I/O refresh.SOLUTION: A programmable controller 1 includes: a first CPU 11 and a second CPU 12 which share a cache memory 19 with each other: and an external interface 17 that transmits and receives data with an external I/O unit 25. The external interface 17 compares an input data from the I/O unit 25 and a data of address for storing the input data in a data memory 20. Only when both are different from each other, the input data is stored in the data memory 20, and the data is updated, and the data corresponding to the updated data in the cache memory 19 is invalidated. |
