MODE-CHANGEABLE DUAL DATA RATE RANDOM ACCESS MEMORY DRIVER WITH ASYMMETRIC OFFSET AND MEMORY INTERFACE INCORPORATING THE SAME

摘要

A memory driver, a method of driving a command bus for a synchronous dual data rate (sDDR) memory and a memory controller for controlling dynamic random-access memory (DRAM). In one embodiment, the memory driver includes: (1) pull-up and pull-down transistors couplable to a command bus of a memory controller and operable in 1N and 2N timing modes and (2) gear down offset circuitry coupled to the pull-up transistor and operable to offset the command bus when transitioning out of the 1N timing mode and increase an extent and duration of 1-0-1 transitions on the command bus.

主权项

1. A memory driver, comprising:
pull-up and pull-down transistors couplable to a command bus of a memory controller and operable in 1N and 2N timing modes; and gear down offset circuitry coupled to said pull-up transistor and operable to offset said command bus when transitioning out of said 1N timing mode and increase an extent and duration of 1-0-1 transitions on said command bus.