SUB-BLOCK DISABLING IN 3D MEMORY

摘要

Some embodiments relate to apparatuses and methods associated with blocks of memory cells. The blocks of memory cells may include two or more sub-blocks of memory cells. One such sub-block may comprise a vertical string of memory cells including a select transistor. An apparatus may include a sub-block disabling circuit. The sub-block disabling circuit may include a content-addressable memory. The content-addressable memory may receive an address, including a block address and a sub-block address. The content addressable memory may output a signal to disable a tagged sub-block if the received address includes the block address and the sub-block address associated with the tagged sub-block. The sub-block disabling circuit may further include a plurality of drivers to drive one or more of the select transistors based on the signal. Other apparatus and methods are described.

主权项

1. An apparatus comprising:
a plurality of blocks of memory cells, at least one of the plurality of blocks including two or more sub-blocks; and a sub-block disabling circuit including a memory to store a block address and sub-block address associated with a sub-block determined to be defective, wherein the sub-block disabling circuit is configured to disable a sub-block associated with the stored block address and sub-block address responsive to receiving a block address and sub-block address that matches the stored block address and sub-block address.