| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide a semiconductor device which uses a surrounding Gate Transistor (SGT) that is a vertical transistor to form an SGT-NAND flash memory decoder in a small area.SOLUTION: In a row selection decoder composed of MOS transistors for selectively connecting a plurality of selection signal lines to a row selection line of a SGT-NAND flash memory, the MOS transistors are formed on a planar silicon layers 102na formed on a substrate and a drain, a gate and a source are arranged in a vertical direction. The gate 106 has a structure to surround a silicon column 104p. The planar silicon layer 102na is composed of a first drain region having a first conductivity type and a second drain region having a second conductivity type, and the first drain region and the second drain region are connected with each other through a silicon layer formed on a surface of the planar silicon layer 102na.</p> |
