AUTO-PHASE SYNCHRONIZATION IN DELAY LOCKED LOOPS

摘要

Tuning circuitry may include a controller that is configured to determine a phase difference for a pair of signals generated at different points in a master delay line of a master-slave delay locked loop (DLL) circuit. One of signals of the pair may be communicated through a slave delay line of the master-slave DLL circuit before the phase difference is determined. A programming delay value used to set a phase delay of the slave delay line may be adjusted or tuned based on the phase difference.

主权项

1. A circuit configured to adjust a programming delay value used to set a phase delay of a slave delay line of a master-slave delay locked loop (DLL) circuit, the circuit comprising:
a controller configured to:
determine a phase difference between a pair of master delay line signals generated at different points of a master delay line of the master-slave DLL circuit, wherein one of the master delay line signals of the pair is communicated through the slave delay line before the phase difference is determined;adjust a programming delay value based on the phase difference to generate an adjusted programming delay value; andoutput the adjusted programming delay value to a bias generator that generates an output bias based on the adjusted programming delay value and supplies the output bias to the slave delay line to set a phase delay of the slave delay line.