发明名称 |
CLOCK GENERATION SYSTEM WITH DYNAMIC DISTRIBUTION BYPASS MODE |
摘要 |
In some embodiments, a tight loop mode is provided is which most, if not all of, the clock distribution circuitry may be bypassed during an initial frequency lock stage. |
申请公布号 |
US2015214959(A1) |
申请公布日期 |
2015.07.30 |
申请号 |
US201314126005 |
申请日期 |
2013.06.28 |
申请人 |
INTEL CORPORATION |
发明人 |
Feldman Allan;Kurd Nasser;Neidengard Mark;Grossnickle Vaughn;Mosalikanti Praveen |
分类号 |
H03L7/08;H03L7/083 |
主分类号 |
H03L7/08 |
代理机构 |
|
代理人 |
|
主权项 |
1. An apparatus, comprising:
a PLL (phase locked loop) circuit to generate a PLL clock at a PLL clock output, the PLL having a feedback path input; a clock distribution circuit switchably coupled to the PLL clock output to generate a post clock off of the PLL clock; and a switch circuit capable of dynamically switching between the PLL clock and the post clock to be coupled to the feedback path input while the pll is generating a clock output. |
地址 |
Santa Clara CA US |