| 发明名称 |
DUTY RATIO CORRECTION CIRCUIT AND PHASE SYNCHRONIZATION CIRCUIT |
| 摘要 |
A duty ratio correction circuit includes: a buffer circuit configured to generate a second signal based on a first signal, the second signal having a DC component corresponding to a first control signal; a waveform shaping section configured to shape a waveform of the second signal to generate a third signal that is a target of duty ratio correction; a first capacitor; and a first charge-discharge control circuit configured to selectively charge or discharge the first capacitor based on the third signal, to generate the first control signal. |
| 申请公布号 |
US2015214932(A1) |
申请公布日期 |
2015.07.30 |
| 申请号 |
US201414566837 |
申请日期 |
2014.12.11 |
| 申请人 |
Sony Corporation |
发明人 |
Tomita Kazutoshi;Harada Shingo;Niwa Atsumi |
| 分类号 |
H03K3/017;H03L7/08 |
主分类号 |
H03K3/017 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A duty ratio correction circuit comprising:
a buffer circuit configured to generate a second signal based on a first signal, the second signal having a DC component corresponding to a first control signal; a waveform shaping section configured to shape a waveform of the second signal to generate a third signal that is a target of duty ratio correction; a first capacitor; and a first charge-discharge control circuit configured to selectively charge or discharge the first capacitor based on the third signal, to generate the first control signal. |
| 地址 |
Tokyo JP |
