发明名称 |
PHASE INTERPOLATION CLOCK GENERATOR AND PHASE INTERPOLATION CLOCK GENERATING METHOD |
摘要 |
A phase interpolation clock generator includes: a phase detector configured to detect a phase difference between an input signal and a clock; a phase control signal generator configured to generate a phase control signal that is inverted for a certain phase difference and changes between a high level and a low level based on the phase difference; a controller configured to generate a combining control signal for combining a plurality of phase clocks and performing phase interpolation based on the phase control signal; an overshoot detector configured to detect overshoot in which the phase control signal rises above the high level; an overshoot canceller configured to lower the phase control signal which rises above the high level at an occurrence of the overshoot; and a phase interpolator configured to generate the clock by combining the plurality of phase clocks in accordance with the combining control signal. |
申请公布号 |
US2015214940(A1) |
申请公布日期 |
2015.07.30 |
申请号 |
US201414572715 |
申请日期 |
2014.12.16 |
申请人 |
FUJITSU LIMITED |
发明人 |
SHIBASAKI Takayuki;Tsunoda Yukito |
分类号 |
H03K5/135 |
主分类号 |
H03K5/135 |
代理机构 |
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代理人 |
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主权项 |
1. A phase interpolation clock generator comprising:
a phase detector configured to detect a phase difference between an input signal and a clock; a phase control signal generator configured to generate a phase control signal that is inverted for a certain phase difference and changes between a high level and a low level based on the phase difference; a controller configured to generate a combining control signal for combining a plurality of phase clocks and performing phase interpolation based on the phase control signal; an overshoot detector configured to detect overshoot in which the phase control signal rises above the high level; an overshoot canceller configured to lower the phase control signal which rises above the high level at an occurrence of the overshoot; and a phase interpolator configured to generate the clock by combining the plurality of phase clocks in accordance with the combining control signal. |
地址 |
Kawasaki-shi JP |