MEMORY DEVICES AND CONTROL METHODS THEREOF

摘要

A memory device includes a first signal line; a memory cell array divided into a first area and a second area and having a plurality of first memory cells and second memory cells in the first area and second area, respectively. The plurality of first and second memory cells are coupled the first signal line, and each has a reference node. A first voltage adjustment circuit adjusts voltages at the reference nodes of the plurality of first memory cells, wherein the first voltage adjustments circuit includes: a first switch coupled between the reference nodes of the plurality of first memory cells and the ground, controlled by an address signal; and a first bias element coupled to the reference nodes of the plurality of first memory cells. A second voltage adjustment circuit adjusts voltages at the reference nodes of the plurality of second memory cells.

主权项

1. A memory device comprising:
a first signal line; a memory cell array divided into a first area and a second area and comprising a plurality of first memory cells in the first area and a plurality of second memory cells in the second area, wherein the plurality of first and second memory cells are coupled the first signal line, and each of the plurality of first and second memory cells has a reference node; a first voltage adjustment circuit for adjusting voltages at the reference nodes of the plurality of first memory cells, the first voltage adjustments circuit comprises: a first switch coupled between the reference nodes of the plurality of first memory cells and the ground, controlled by an address signal, wherein the address signal indicates that the memory device is performing an access operation to the first area or the second area; and a first bias element coupled to the reference nodes of the plurality of first memory cells; and a second voltage adjustment circuit for adjusting voltages at the reference nodes of the plurality of second memory cells; wherein, the reference nodes of the plurality of first memory cells are coupled to a ground through the first voltage adjustment circuit, and the reference nodes of the plurality of second memory cells are coupled to the ground through the second voltage adjustment circuit.