ARRAY SUBSTRATE, DISPLAY DEVICE AND CONTROL METHOD THEREOF

摘要

An array substrate, a display device and a control method thereof are disclosed. The array substrate includes a plurality of gate lines and a plurality of data lines which are intercrossed to define pixels arranged in an array. The gate lines include n gate line groups and n+1 main gate lines; each gate line group includes a first gate line and a second gate line which are adjacent to each other; the first gate line is provided corresponding to a first transistor, and the second gate line is provided corresponding to a second transistor and a switching element; both the first gate line and the second gate line in the ith gate line group are connected with the ith main gate line; a gate electrode of the first transistor is connected with the first gate line, a source electrode connected with a corresponding data line, a drain electrode connected with a pixel electrode; a gate electrode of the second transistor is connected with one end of the switching element in a pixel unit, a source electrode connected with a corresponding data line, a drain electrode connected with a pixel electrode; and the other end of the switching element is connected with a main gate line in the (i+1)th row and configured to control on/off operation of the second transistor.

主权项

1. An array substrate, comprising a plurality of gate lines and a plurality of data lines which are intercrossed to define pixels arranged in an array,
wherein the plurality of gate lines include n gate line groups and n+1 main gate lines; each gate line group includes a first gate line and a second gate line which are adjacent to each other; the first gate line is provided corresponding to a first pixel group, and the second gate line is provided corresponding to a second pixel group; the first pixel group includes a plurality of first pixel units arranged in a row; each first pixel unit includes a first transistor; the second pixel group includes a plurality of second pixel units arranged in a row; the second pixel unit includes a second transistor and a switching element; both the first gate line and the second gate line in the ith gate line group are connected with the ith main gate line; in the first pixel unit corresponding to the first gate line in the ith gate line group, a gate electrode of the first transistor is connected with the first gate line; a source electrode of the first transistor is connected with a corresponding data line; a drain electrode of the first transistor is connected with the pixel unit; in the second pixel unit corresponding to the second gate line in the ith gate line group, a gate electrode of the second transistor is connected with one end of the switching element in the pixel unit; a source electrode of the second transistor is connected with a corresponding data line; a drain electrode of the second transistor is connected with a pixel electrode of the pixel unit; and in the second pixel unit corresponding to the second gate line in the ith gate line group, another end of the switching element is connected with a main gate line in the (i+1)th row or any gate line in the (i+1)th gate line group and configured to control on/off operation of the second transistor in the second pixel unit in the ith gate line group, in which both i and n are integers, and 1≦i≦N.