发明名称 MEMORY DEVICE HAVING STITCHED ARRAYS OF 4 F+hu 2 +l MEMORY CELLS
摘要 A memory device comprises a semiconductor substrate having a plurality of parallel trenches therein, a memory region formed in the substrate including an array of memory cells having a plurality of vertical selection transistors with respective channels formed in trench sidewalls, a plurality of buried source electrodes in trench bottoms, a plurality of paired gate electrodes formed on paired trench sidewalls, a first and second stitch region disposed adjacent the memory region along a trench direction including a first and second row of gate contacts, respectively, and a row of source contacts disposed in the first or second stitch region with each of the source contacts coupled to a respective one of the source electrodes. One of each pair of the gate electrodes is coupled to a respective one of the first row of gate contacts and the other one of each pair of gate electrodes is coupled to a respective one of the second row of gate contacts.
申请公布号 US2015214278(A1) 申请公布日期 2015.07.30
申请号 US201514685196 申请日期 2015.04.13
申请人 Avalanche Technology, Inc. 发明人 Satoh Kimihiro;Zhang Jing;Huai Yiming
分类号 H01L27/24;H01L45/00;H01L43/08;H01L27/22;H01L43/02 主分类号 H01L27/24
代理机构 代理人
主权项 1. A memory device comprising: a plurality of memory arrays formed along a first direction, each of said memory arrays including: a memory region comprising a set of memory cells arranged in an array with a first pitch in a second direction substantially perpendicular to said first direction; anda first stitch region and a second stitch region disposed adjacent said memory region along said first direction having respectively a first row and a second row of gate contacts disposed therein, each row of said first and second rows of gate contacts extending along said second direction, gate contacts in said each row having a second pitch that is about twice said first pitch, each gate contact of said first and second rows of gate contacts being connected to a respective row of said set of memory cells along said first direction; and a first and second plurality of word lines extending along said first direction, wherein each row of said first and second rows of gate contacts of each of said memory arrays is coupled to said first or second plurality of word lines.
地址 Fremont CA US