PARTITIONED RESISTIVE MEMORY ARRAY

摘要

A resistive memory array partitioned into a plurality of memory units is disclosed. Each memory unit includes a plurality of resistive memory elements, a plurality of row lines, a plurality of column lines, a plurality of row select switching devices, and a plurality of column select switching devices. Each resistive memory element is in communication with one of the row lines and one of the column lines. Each row line is in communication with a corresponding one of the row select switching devices. Each column line is in communication with a corresponding one of the column select switching devices.

主权项

1. A resistive memory device, comprising:
a resistive memory array partitioned into a plurality of memory units, wherein each memory unit includes:
a plurality of resistive memory elements;a plurality of row lines, wherein each resistive memory element is in communication with one of the row lines;a plurality of column lines, wherein each resistive memory element is in communication with one of the column lines;a plurality of row select switching devices, wherein each row line is in communication with a corresponding one of the row select switching devices; anda plurality of column select switching devices, wherein each column line is in communication with a corresponding one of the column select switching devices.