MULTI-LEVEL CELL DESIGNS FOR HIGH DENSITY LOW POWER GSHE-STT MRAM

摘要

Systems and methods are directed to multi-level cell (MLC) comprising: two or more programmable elements coupled to a common access transistor, wherein each one of the two or more programmable elements has a corresponding unique set of two or more switching resistances and two or more switching currents characteristics, such that combinations of the two or more programmable elements configured in the respective two or more switching resistance correspond to multi-bit binary states controllable by passing switching currents through the common access transistor. Each one of the two or more programmable elements includes one or more hybrid giant spin Hall effect (GSHE)-spin transfer torque (STT) magnetoresistive random access memory (MRAM) cell, with two or more hybrid GSHE-STT MRAM cells coupled in parallel.

主权项

1. A multi-level cell (MLC) comprising:
one or more programmable elements coupled to a common access transistor, wherein each one of the one or more programmable elements has a unique pair of switching resistances corresponding to two binary states respectively, wherein, the switching resistances are provided by hybrid giant spin Hall effect (GSHE)-spin transfer torque (STT) magnetoresistive random access memory (MRAM) elements.