| 摘要 |
Disclosed are a driving circuit for a gate and a common electrode. The driving circuit comprises a trigger (602), a first selection input circuit (603), a second selection input circuit (601), a third selection input circuit (604), a fourth selection input circuit (605), and a selection output circuit (606). The first selection input circuit (603) is used for selecting an (n-1)th gate line signal (G[n-1]) and a (n+2)th gate line signal (G[n+2]) to an input end (1) of the trigger (602). The second selection input circuit (601) is used for separately connecting a common electrode high level input (Com_2) and a gate high level input (Vgh) to a clock end (2) of the trigger (602) under different time sequences to upwards pull a voltage at the trigger output end (5). The third selection input circuit (604) is used for selecting an (n+1)th gate line signal (G[n+1]) and an (n+4)th gate line signal (G[n+4]) to a reset end (3) of the trigger (602). The fourth selection input circuit (605) is used for separately connecting a gate low level input (Vss) or a common electrode low level input (Com_1) to a low level input end (4) of the trigger (602) under the control of the (n+1)th gate line signal (G[n+1]) and the (n+4)th gate line signal(G[n+4]) to pull a voltage at the input end (4) downwards. The selection output circuit (606) is used for selecting to output an nth gate line signal (G[n]) or an (n+3)th common electrode line signal (C[n+3]) at different pulse time sequences f. By means of the driving circuit, the common electrode output is synchronized with the gate, and is opposite to the gate in the voltage changing direction, and a feed-through voltage is effectively counteracted. Also disclosed are a display panel driving circuit an array substrate. |
