发明名称 Hardware peripheral decoders
摘要 An integrated circuit comprises at least two inputs 18, 20, and a decoder 24 arranged to sample 28 said inputs in a first cycle and sample said inputs in a second, later cycle. A first memory location 34 is altered if only one of said sampled inputs changes from the first cycle to the second cycle, and a second memory location 46 is altered if both of said sampled inputs change from the first cycle to the second cycle. The decoder may generate an interrupt signal to a CPU if the first memory location and/or the second memory location is altered. The decoder may be for decoding inputs from a hardware peripheral device such as a wireless computer mouse. The inputs may be quadrature signals from an optical rotary encoder detecting movement from a scroll wheel. The decoder may be a quadrature decoder.
申请公布号 GB201510557(D0) 申请公布日期 2015.07.29
申请号 GB20150010557 申请日期 2015.06.16
申请人 NORDIC SEMICONDUCTOR ASA 发明人
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