| 摘要 |
<p>The present invention relates to a clock doubler. The clock doubler includes: a clock cycle detection unit which delays a clock signal at a first frequency through multiple unit delay circuits and detects the number of the unit delay circuits used for the unit delay of the clock signal; and a clock generation unit which generates another clock signal delayed by half of the original clock signal′s cycle in response to the signal output from the clock cycle detection unit and generates another clock signal at a second frequency having a cycle corresponding to the clock edge of the original clock signal and the delayed clock signal.</p> |
