Phase locked loop with the ability to accurately apply phase offset corrections while maintaining the loop filter characteristics

摘要

A digital phase locked loop has a phase acquisition module that outputs a first phase value representative of the phase of a reference signal expressed with respect to an internal phase reference. A phase offset write module convert a phases offset commanded from an external source into a phase offset correction value expressed with respect to the internal phase reference. A phase offset controller sums the phase offset correction values to produce a second phase value, which is added to the first phase value to produce a third phase value expressed with respect to the internal phase reference. A digital controlled oscillator (DCO) outputs a fourth phase value expressed with respect to the internal phase reference. A phase detector outputs a fifth phase value representing the difference between the third and fourth phase values. A loop filter derives a frequency offset for the DCO based on the fifth phase value. An output module generates one or more output clocks from the fourth phase value.

主权项

1. A digital phase locked loop, comprising:
a phase acquisition module configured to output a first phase value representative of the phase of a reference signal expressed with respect to an internal phase reference; a phase offset write module configured to convert a phase offset commanded from an external source into a phase offset correction value expressed with respect to said internal phase reference; a phase offset controller for summing said phase offset correction values from said phase offset write module to produce a second phase value; an adder for adding said second phase value to said first phase value to produce a third phase value; a digital controlled oscillator (DCO) configured to output a fourth phase value expressed with respect to said internal phase reference; a phase detector for outputting a fifth phase value representing the difference between said third and fourth phase values; a loop filter configured to derive a frequency offset for said DCO based on said fifth phase value; and an output module configured to generate one or more output clocks from said fourth phase value.