Integrated circuit packaging system with exposed vertical interconnects and method of manufacture thereof

摘要

A method of manufacture of an integrated circuit packaging system includes: providing a substrate; attaching an integrated circuit to the substrate; attaching a vertical interconnect over the substrate; forming an encapsulation on the substrate and covering the vertical interconnect; and forming a rounded cavity, having a curved side, in the encapsulation with the vertical interconnect exposed in the rounded cavity.

主权项

1. A method of manufacture of an integrated circuit packaging system comprising:
providing a substrate; attaching an integrated circuit to the substrate; attaching a vertical interconnect having a convex top portion over the substrate, wherein the vertical interconnect having characteristics of removal of an interconnect cap of a material different from the vertical interconnect; forming an encapsulation, on the substrate, having an encapsulation top side exposed above the convex top portion of the vertical interconnect; and forming a rounded cavity in the encapsulation, between the encapsulation top side and the vertical neck wherein the rounded cavity includes a cavity opening at the encapsulation top side, the cavity opening directly above the convex top portion of the vertical interconnect, exposing the convex top portion of the vertical interconnect through the cavity opening.