Methods of forming electronic elements with ESD protection

摘要

An electrostatic discharge (ESD) protection circuit (40) is coupled across input-output (I/O) pads (21) and common terminals (24) of a circuit core (22) to protect it from ESD events. The circuit (40) comprises, a unidirectional ESD clamp (23) and two or more floating diodes (42, 44) arranged in parallel opposed configuration in series with the ESD clamp (23), the combination coupled between the I/O pads (21) and the reference terminals (24). In a preferred arrangement, the two strings of opposed parallel coupled diodes (42, 44) are used with different numbers of diodes in each string. These diodes (42, 44) operate in forward conduction (43, 45), so the energy dissipated therein during an ESD event is much reduced compared to a reverse biased diode and they can have smaller area. Signal clipping at the I/O pad (21) is reduced, less power is dissipated and less chip area is utilized.

主权项

1. A method for forming an electronic element, comprising:
providing a substrate on or in which has been formed a circuit core having first and second terminals desired to be protected from electrostatic discharge (ESD) events and an asymmetrical ESD protection device having third and fourth terminals, the substrate having an insulating first surface region; depositing on the first surface region of the substrate a polycrystalline semiconductor (PSC) layer; in a first portion of the PSC layer, forming N diodes by localized doping of the PSC layer, wherein the PSC layer has therein N+(N−1) PN junctions of which (N−1) are shorted together; in a second portion of the PSC layer, forming M diodes by localized doping of the PSC layer, wherein the PSC layer has therein M+(M−1) PN junctions of which (M−1) are shorted together; and electrically coupling the N diodes and M diodes in opposed parallel configuration between the first terminal of the circuit core and the third terminal of the ESD protection device, and coupling the fourth terminal of the ESD protection device to the second terminal of the circuit core.