| 发明名称 | Semiconductor memory device | ||
| 摘要 | According to one embodiment, a semiconductor memory device includes: a memory cell array; a first data latch; a second data latch; a first data bus; a second data bus; a first temporary latch; a second temporary latch; and a control unit. The first and the second data latches are electrically connected to the memory cell array. The first data bus is electrically connected to the first data latch. The second data bus is electrically connected to the second data latch. The first temporary latch is electrically connected to the first data bus. The second temporary latch is electrically connected to the second data bus. The control unit is configured to write data on the first temporary latch and transfer data retained in the first temporary latch to the first data latch while writing data on the second temporary latch. | ||
| 申请公布号 | US9093159(B2) | 申请公布日期 | 2015.07.28 |
| 申请号 | US201414206631 | 申请日期 | 2014.03.12 |
| 申请人 | Kabushiki Kaisha Toshiba | 发明人 | Takagiwa Teruo;Ogawa Masatsugu |
| 分类号 | G11C11/34;G11C16/10 | 主分类号 | G11C11/34 |
| 代理机构 | Oblon, McClelland, Maier & Neustadt, L.L.P. | 代理人 | Oblon, McClelland, Maier & Neustadt, L.L.P. |
| 主权项 | 1. A semiconductor memory device comprising: a memory cell array including a plurality of memory cells; a first data latch electrically connected to the memory cell array; a second data latch electrically connected to the memory cell array; a first data bus electrically connected to the first data latch; a second data bus electrically connected to the second data latch; a first temporary latch electrically connected to the first data bus; a second temporary latch electrically connected to the second data bus; and a control unit configured to write data on the first temporary latch and transfer data retained in the first temporary latch to the first data latch while writing data on the second temporary latch. | ||
| 地址 | Minato-ku JP | ||