| 摘要 |
An entropy storage ring includes an input node, a plurality of serial-connected stages, and an output node. Each stage includes an XOR (or XNOR) circuit, a delay element having an input coupled to the XOR output, and a combinatorial circuit having an output coupled to a second input of the XOR. The combinatorial circuit may be a NAND, NOR, AND or OR gate. A first input of the XOR is the data input of the stage. The output of the delay element is the data output of the stage. A first input of the combinatorial circuit is coupled to receive an enable bit from a configuration register. A second input of the combinatorial circuit is coupled to the ring output node. In operation, a bit stream is supplied onto the ring input node. Feedback of multiple stages are enabled so that the bit stream undergoes complex permutation as it circulates. |
| 主权项 |
1. A circuit comprising:
a configuration register that outputs a plurality of enable bit signals; and signal storage ring comprising:
a signal storage ring input node;a signal storage ring output node; anda plurality of stages, wherein each of at least two of the stages comprises:an exclusive OR circuit having a first input lead, a second input lead, and an output lead, wherein the first input lead of the exclusive OR circuit is a ring data input of the stage;a combinatorial logic circuit having a first input lead, a second input lead, and an output lead, wherein the output lead of the combinatorial logic circuit is coupled to the second input lead of the exclusive OR circuit, wherein the second input lead of the combinatorial logic circuit is coupled to the signal storage ring output node, wherein the first input lead of the combinatorial logic circuit is coupled to receive one of the enable bit signals; anda delay element having an input lead and an output lead, wherein the input lead of the delay element is coupled the output lead of the exclusive OR circuit, wherein the output lead of the delay element is a ring data output of the stage, and wherein the delay element is taken from the group consisting of: a single inverter, an odd number of series-connected inverters, an even number of series-connected inverters. |
