Address mapped repartitioned digital pixel

摘要

By adding stabilization and super-sampling to a digital pixel readout integrated circuit (ROIC), line of sight motion, that is usually costly and difficult to control, instead becomes an ally, doubling the effective FPA resolution in some systems. The base repartitioned digital pixel architecture supplements analog signal accumulation with off-pixel digital accumulation, greatly increasing dynamic range. Adding address mapping and increasing the ratio of memory locations to pixels, enables stabilization and resolution enhancement. Additional stabilization at sub-frame intervals limits the effect of latency and simplifies complex address mapping. Pixels gains are compensated in-ROIC, without requiring multipliers. A unique partitioning of functions between the ROIC and subsequent logic allows pixel biases and non-isomorphic sampling effects to be compensated off-ROIC, reducing overall system complexity and power.

主权项

1. A read out circuit for an array of detector elements, said read out circuit comprising:
an array of pixel cells, each of the pixel cells including:
a storage device configured to accumulate a value in response to radiation impinging on a corresponding detector element;quantization circuitry configured to compare the accumulated value to a threshold value and generate a quantization event;a logical output configured to report the quantization event; anda compensator circuit configured to reduce the accumulated value on the storage device to account for the reported quantization event; at least one digital memory disposed physically separate from the array of pixel cells, said at least one digital memory comprising a plurality of addressable memory locations configured to store digital values; an address mapping input configured to receive updates to an address mapping signal during a frame integration interval, said updated address mapping signal providing a mapping between the pixel cells and the memory locations; and a control circuit disposed physically separate from the array of pixel cells, said control circuit including:
a shared quantization event selector configured to identify the pixels for which a quantization event is reported and to initiate memory updates for those pixels;an address generator configured to determine a memory location for each memory update based on the updated address-mapping signal;memory update logic configured to modify the digital value of the corresponding memory location for each memory update; andoutput logic configured to output digital values accumulated over the frame integration interval from at least some of the memory locations.