发明名称 Systems and methods for sending and receiving information via a network device
摘要 A network device is provided. The network device includes a port complex having a plurality of ports configured to operate at different operating speeds for sending and receiving information complying with different protocols. The network device further includes a processor complex having a plurality of processors for processing information complying with different protocols and received by the plurality of ports; and a message queuing system (MQS) for managing messages for the plurality of processors regarding the received information complying with different protocols. Each processor can process information complying with any of the different protocols.
申请公布号 US9094333(B1) 申请公布日期 2015.07.28
申请号 US201113328919 申请日期 2011.12.16
申请人 QLOGIC, Corporation 发明人 Klemin Bruce A.;Alston Jerald K.;Rohde Derek J.
分类号 H04L12/00;H04L12/931;H04L12/935 主分类号 H04L12/00
代理机构 Klein, O'Neill & Singh, LLP 代理人 Klein, O'Neill & Singh, LLP
主权项 1. An adapter coupled to a host computing device for sending and receiving information, comprising: a port complex having: a plurality of ports configured to operate at different operating speeds for sending and receiving frames complying with different protocols, where the plurality of ports send frames on behalf of the host computing device and receive frames from other devices; andan arbiter that selects one of the received frames for processing after the received frames are stored at arbiter temporary storage locations, wherein when a frame is encrypted, the arbiter first sends the frame to a decryption module of the port complex and after the frame is decrypted, the decrypted frame is selected by the arbiter for processing; a processor complex having a plurality of processors for processing frames complying with different protocols and received by any of the plurality of ports; wherein each processor of the processor complex can process frames complying with any of the different protocols and originating from any of the plurality of ports; a message queuing system (MQS) interfacing with the port complex and the processor complex for managing messages for the plurality of processors regarding the received frames complying with different protocols; a general processor for configuring the adapter; and a memory interface module that manages requests from any processor of the processor complex; the general processor and any component of the port complex to access a local adapter memory and a host computing device memory for processing received frames, transmitting frames and configuring the adapter; wherein an arbiter of the memory interface module arbitrates between requests for the local adapter memory and the host computing device memory.
地址 Aliso Viejo CA US