| 发明名称 | Circuits for receiving data | ||
| 摘要 | A receiving circuit includes a clock input portion configured to buffer a first pattern signal and configured to retard the buffered first pattern signal by a first delay time to generate an input clock signal, a data input portion configured to buffer a second pattern signal and configured to retard the buffered second pattern signal by a second delay time to generate an input data signal, and a comparator configured to compare a phase of the input clock signal with a phase of the input data signal to generate a comparison signal for adjusting the second delay time. | ||
| 申请公布号 | US9094183(B2) | 申请公布日期 | 2015.07.28 |
| 申请号 | US201213719001 | 申请日期 | 2012.12.18 |
| 申请人 | SK hynix Inc. | 发明人 | Byeon Sang Yeon |
| 分类号 | H04L7/02;H04L7/033;H04L7/00 | 主分类号 | H04L7/02 |
| 代理机构 | Kilpatrick Townsend & Stockton LLP | 代理人 | Kilpatrick Townsend & Stockton LLP |
| 主权项 | 1. A receiving circuit comprising: a clock input portion configured to buffer a first pattern signal and configured to retard the buffered first pattern signal by a first delay time to generate an input clock signal; a data input portion configured to buffer a second pattern signal and configured to retard the buffered second pattern signal by a second delay time to generate an input data signal; a comparator configured to compare a phase of the input clock signal with a phase of the input data signal to generate a comparison signal for adjusting the second delay time; and an internal data output portion configured to latch the input data signal in synchronization with the input clock signal to generate an internal data signal. | ||
| 地址 | Icheon-si KR | ||