Data cache virtual hint way prediction, and applications thereof

摘要

A virtual hint based data cache way prediction scheme, and applications thereof. In an embodiment, a processor retrieves data from a data cache based on a virtual hint value or an alias way prediction value and forwards the data to dependent instructions before a physical address for the data is available. After the physical address is available, the physical address is compared to a physical address tag value for the forwarded data to verify that the forwarded data is the correct data. If the forwarded data is the correct data, a hit signal is generated. If the forwarded data is not the correct data, a miss signal is generated. Any instructions that operate on incorrect data are invalidated and/or replayed.

主权项

1. A processor comprising:
a memory; and logic configured to:
store virtual address tag bits and physical address tag bits in a first portion of the memory,store data bits in a second portion of the memory,store alias way prediction values for execution of an instruction in a third portion of the memory,store exception values in a fourth portion of the memory, each exception value including exception-specific information, andstore identification values in a fifth portion of the memory, each identification value based on a completion buffer identification value of a particular instruction,wherein an alias way prediction value is forwarded to an execution unit when no match exists between selected bits of a virtual address and the virtual address tag bits stored in the first portion of the memory at locations indexed by bits of the virtual address, and wherein upon a cache hit for a cache line using a way, the cache hit indicating physical address tag bits for data retrieved using the way match physical address tag bits associated with a virtual address associated with the used way, a corresponding line in the third portion of the memory is updated with a value corresponding to the used way.