Instrumentation of hardware assisted transactional memory system

摘要

Monitoring performance of one or more architecturally significant processor caches coupled to a processor. The methods include executing an application on one or more processors coupled to one or more architecturally significant processor caches, where the application utilizes the architecturally significant portions of the architecturally significant processor caches. The methods further include at least one of generating metrics related to performance of the architecturally significant processor caches; implementing one or more debug exceptions related to performance of the architecturally significant processor caches; or implementing one or more transactional breakpoints related to performance of the architecturally significant processor caches as a result of utilizing the architecturally significant portions of the architecturally significant processor caches.

主权项

1. In a computing environment, a method of monitoring performance of one or more processor caches coupled to a processor, the method comprising:
executing an application on one or more processors coupled to the one or more processor caches, wherein the application utilizes one or more portions of the one or more processor caches; establishing a buffer monitor entry and at least one of a read monitor entry and a write monitor entry, each monitor entry being established on a cache line basis for a particular thread, the read monitor entry indicating whether a read monitor is to monitor a data block to determine when data is written to the data block by another thread, the write monitor entry indicating whether a write monitor is to monitor the data block to determine when data is read from or written to the data block by another thread, the buffer monitor entry indicating whether the data is buffered data or cached data, and whether data buffering has been lost for a specified transaction; determining that execution of the application has caused the read monitor, the write monitor or the buffer monitor to be reset, indicating that execution of the application has reached a potential bottleneck; determining the amount of the specified transaction that is executed after the transaction has been indicated as doomed as a result of a read, write or buffer monitor being reset, the amount of execution being determined by sampling a hardware performance counter before and after the specified transaction and subtracting the before sample from the after sample; and generating metrics related to performance of the one or more processor caches as a result of utilizing the one or more portions of the one or more processor caches, including incrementing a counter that tallies the number of times that the read monitor, the write monitor or the buffer monitor has been reset.