Three dimensional image display

摘要

A three-dimensional (“3D”) image display includes a signal controller which receives two-dimensional (“2D”) image information and 3D image information and generates control signals based on the 2D image information and the 3D image information, a clock generator which receives the control signals from the signal controller and generates a first clock signal corresponding to the 3D image information and a second clock signal corresponding to the 2D image information, and a gate driver which generates a gate-on voltage based on at least one of the first clock signal and the second clock signal, where a frequency of the second clock signal is lower than a frequency of the first clock signal and an amplitude of the second clock signal is less than an amplitude of the first clock signal.

主权项

1. A three-dimensional image display comprising:
a signal controller which receives two-dimensional image information and three-dimensional image information and generates control signals based on the two-dimensional image information and the three-dimensional image information; a clock generator which receives the control signals from the signal controller and generates a first clock signal corresponding to the three-dimensional image information and a second clock signal corresponding to the two-dimensional image information; and a gate driver which generates a gate-on voltage based on at least one of the first clock signal and the second clock signal, wherein a frequency of the second clock signal is lower than a frequency of the first clock signal, and an amplitude of the second clock signal is less than an amplitude of the first clock signal, and wherein the control signals includes a first clock enable signal, a second clock enable signal, a first clock control signal and a second clock control signal, the clock generator generates the first clock signal based on the first clock enable signal and the first clock control signal and generates the second clock signal based on the second clock enable signal and the second clock control signal, and a rising edge of the first clock enable signal occurs when the first clock control signal has a low level value, and a rising edge of the second clock enable signal occurs when the second clock control signal has a low level value, and the electric charge sharing time of the first clock signal corresponds to a time period between a falling edge of the first clock control signal and a rising edge of the first clock enable signal, and the electric charge sharing time of the second clock signal corresponds to a time period between a falling edge of the second clock control signal and a rising edge of the second clock enable signal.