Functional unit for vector leading zeroes, vector trailing zeroes, vector operand 1s count and vector parity calculation

摘要

A method of performing vector operations on a semiconductor chip is described. The method includes performing a first vector instruction with a vector functional unit implemented on the semiconductor chip and performing a second vector instruction with the vector functional unit. The first vector instruction is a vector multiply add instruction. The second vector instruction is a vector leading zeros count instruction.

主权项

1. A vector functional unit implemented on a semiconductor to perform vector operations of dimension N, comprising:
N functional units, each of the N functional units comprising: a multiplier logic circuit and an adder logic circuit to perform a multiply add operation on respective A, B and C operands responsive to a vector multiply add instruction, the A, B and C operands received on respective inputs of the functional unit; a leading ones count logic circuit downstream from an alignment shifter circuit that precedes said adder logic circuit, said leading ones count logic circuit to perform a leading ones count operation responsive to the vector multiply add instruction to adjust an exponent value for the vector multiply add instruction; and a leading zeros count logic circuit downstream from said alignment shifter circuit to perform a leading zeros count operation on an operand received on one of the respective A, B and C operand inputs, the leading zeros count operation being responsive to a vector leading zeros count instruction.