High temperature equalized electrical parasitic power packaging method for many paralleled semiconductor power devices

摘要

A four quadrant power module with lower substrate parallel power paths and upper substrate equidistant clock tree timing utilizing parallel leg construction in a captive fastener power module housing.

主权项

1. A four quadrant power module, comprising:
a power circuit including power devices arranged in a first quadrant power section, a second quadrant power section, third quadrant power section, and fourth quadrant power section; a first quadrant power section including power devices connected from the first power substrate to the third power substrate, a second quadrant power section including power devices connected from the second power substrate to the fourth power substrate, a third quadrant power section including power devices connected from the third power substrate to the fifth power substrate, a fourth quadrant power section including power devices connected from the fourth power substrate to the sixth power substrate, a first power contact connected to the first power substrate; a second power contact connected to the second power substrate; a third power contact connected to the third power substrate; a fourth power contact connected to the fourth power substrate; a fifth power contact connected to the fifth power substrate; a sixth power contact connected to the sixth power substrate; a first gate source interconnection substrate connected to at least one power device, the first gate source interconnection substrate including a first gate contact and a first source contact; a second gate source interconnection substrate connected to at least one power device, the second gate source interconnection substrate including a second gate contact and a second source contact; a third gate source interconnection substrate connected to at least one power device, the third gate source interconnection substrate including a third gate contact and a third source contact; a fourth gate source interconnection substrate connected to at least one power device, the fourth gate source interconnection substrate including a fourth gate contact and a fourth source contact; each upper interconnection substrate including traces in a clock tree equidistant path layout having at least one central trunks connected to branches.